PROM's are becoming increasingly important in field-programmable electronic memory applications. Of particular importance is the type of PROM containing an array of rows and columns of memory cells that each consist of a pair of back-to-back PN junction diodes. A first of the diodes in each cell serves as an array element for electrically isolating the cell while the second diode is selectively destructible for programming a logical "0" or a logical "1" into the cell. The programmable diode is typically destroyed by forcing a sufficiently high reverse current to flow through its PN junction so as to permanently short circuit this junction.
Electrically insulating material such as silicon dioxide is employed in laterally separating the memory cells in some prior art PROM's using the back-to-back diode configuration. In U.K. patent publication No. 2005079, "Programmable read-only memory cell" corresponding to U.S. Pat. No. 4,229,757, M. Moussie discloses such a PROM in which each array diode is a vertical diode with its PN junction lying horizontally in a monocrystalline silicon region of a semiconductor body and fully laterally adjoining a deep (or recessed) region of silicon dioxide in the body. Each programmable diode is a horizontal diode with its PN junction located in a region of polycrystalline silicon adjoining the monocrystalline region along its upper surface. The PN junction of each programmable diode extends generally perpendicular to the lower surface of the body. This PROM is fabricated by forming an N-type epitaxial layer on the upper surface of a P-type substrate and then forming a P-type epitaxial layer on the N-type epitaxial layer. A deep N-type region contacts the bottom surface of the deep oxide region which is formed around portions of the epitaxial layers to create the array diodes. At each cell there is an aperture through an insulating layer covering the P-type epitaxial layer. The PN junctions for the programmable diodes are formed in a layer of polycrystalline silicon deposited on the insulating layer and on the portions of the P-type epitaxial layer exposed by the apertures.
Even though comparatively small currents of about 20 ma are needed to program this PROM, its horizontal diodes increase cell area. In addition, the properties of PN junctions in polycrystalline silicon are less controllable during manufacture than those in monocrystalline silicon.
T. Fukushima et al disclose another such PROM in European Patent Publication No. 0018173, "A programmable read-only memory device". In each memory cell of this PROM, the PN junctions of both diodes are located in a monocrystalline silicon region. An isolation region which contains silicon dioxide directly adjoining the monocrystalline region laterally separates the cells. Each PN junction is substantially horizontal in the middle of its cell and extends up to the upper surface of the monocrystalline region at a location spaced apart from the side walls of the isolation region. The PN junction of each array diode laterally and upwardly encloses the PN junction of the corresponding programmable diode. This PROM is manufactured by selectively forming N-type tubs along the upper surface of a P-type silicon substrate after which an N-type epitaxial layer is formed on the upper substrate surface. The lateral isolation areas are then formed, and the pairs of PN junctions are created by forming P-type regions in the epitaxial layer over the tubs and forming N-type regions in the P-type regions.
Although this PROM permits the use of shallow regions to define the diodes, the nesting of the diodes in each cell make the cell area comparatively large due to photolithographic alignment tolerances. The memory element occupies about 9 micron.sup.2. This increases the programming current. Furthermore, parasitic transistor action during the programming of a cell in one tub may cause the PN junction between the substrate and another tub along the same column to forward bias so as to damage the programmable diode in the cell along the same column in the other tub.